1. Technical Field
The present invention relates to semiconductor device simulation and more particularly to a method of automating the discretization of two and three dimensional semiconductor device representations.
2. Related Art
Computer based simulations have become an integral part of semiconductor manufacturing because they allow chip designers to study and predict the electrical behavioral characteristics of a semiconductor device before it is ever manufactured. Semiconductor device simulation is increasingly used in the microelectronics industry for reducing hardware experiments and technology development time, for producing more manufacturable and higher-performance designs, and for reducing product time to market. Concommitent with the increased use of simulation is a trend to apply simulation to increasingly complex structures and increasingly complex physical phenomena. Unfortunately, because known simulation techniques require a significant amount of computational resources, severe time and computer processing limitations presently exist.
Semiconductor-device simulation is typically accomplished by first generating a two or three dimensional computer representation of the structure that includes various material regions. Next, the structure is subdivided into a mesh structure that includes numerous grid points which constitute the vertices of the subdivided regions. The mathematical equations describing the physical phenomena that determine the electrical characteristics of the semiconductor device are then solved on the mesh subdivisions. The typical result of the solution is a set of physical quantities defined at each grid point. Typical physical quantities are electric potential, positive and negative carrier concentrations, semiconductor atomic lattice temperature and average carrier temperature. The grid points can then be used to create mathematical equations that describe the characteristics of the device. In general, it is desirable to have a high number of grid points to create an accurate simulation. Unfortunately, as the number of grid points increases, the computation burden of solving the equations also increases.
As noted above, the computation burden of performing simulations is further affected by the fact that silicon devices are becoming more and more complex. For example, beginning with the 16 Mb generation of semiconductor devices, practically all dynamic random access memory (DRAM) cell design issues are three dimensional in nature. Three-dimensional simulation poses an order-of-magnitude greater computational burden compared to the more typical two dimensional simulation.
In addition, silicon-on-insulator (SOI) technology, is becoming increasingly attractive as the drive to denser integrated circuits, composed of smaller devices and utilizing lower power supplies, proceeds. SOI device structures are significantly more complex than the commonly used bulk silicon devices, and the operation is based on physical phenomena that are more complex than those driving bulk devices. Physically accurate simulations of SOI devices may require solution of up to twice the number of equations required by less complex structures.
Moreover, there is a growing demand for a "design-for-manufacturing" (DFM) approach to using simulation. In this approach, hundreds of distinct simulations of a given design point are performed in order to cover the range of perturbations experienced in a manufacturing environment. This approach to simulation obviates the present paradigm in which engineers manually prepare and submit simulations.
Finally, the shrinking dimensions of modem and future transistors makes quantum-mechanical physical effects more and more prevalent. Solving the partial differential equations that describe these effects is a much more computationally intensive process than the semiclassical equations now routinely used to simulate semiconductor device operation.
Thus, without a more efficient method of performing simulations, designing and manufacturing of semiconductor devices will be severely limited. The aforementioned technology references and prior art are herein included by reference.